_____________________________________________________________________________________________________________________________ _________________ dsc2010 page 1 mk - q - b - p - d - 120426 01 - 2 low - jitter configurable cmos oscillator dsc 2010 general description the dsc 201 0 series of high performance cmos oscillators utilize a proven silicon mems technology to provide excellent jitter and stability while incorporating additional device functionality . the dsc2010 allows the user to easily modify the frequency and drive strength of the oscillator using pins. the dsc201 0 has provision for up to four u ser - defined pre - programmed, pin - selectable output frequencies, and eight pin - selectable output drive levels to help reduce emi. dsc201 0 is packaged in a 14 - pin 3.2x2.5 mm qfn package and available in temperature grades from ext. commercial to automotive. block diagram features ? low rms phase jitter: <1 ps (typ) ? high stability: 1 0 , 25, 50 ppm ? wide temp erature range o automotive : - 55 to 125 c o ext. industrial: - 40 to 10 5 c o industrial: - 40 to 85 c o ext. commercial: - 20 to 70 c ? high supply noise rejection: - 50 dbc ? pin - selectable configurations o 3 - bit output drive strength o 2 - bit output frequency combinations ? short lead times: 2 weeks ? wide freq. range: o cmos output: 2.3 to 170 mhz ? miniature footprint of 3.2x2.5mm ? excellent shock & vibration immunity o qualified to mil - std - 883 ? high reliability o 20x better mtf than quartz oscillators ? supply range of 2.25 to 3.6 v ? lead free & rohs compliant applications ? consumer electronics ? storage area networks o sata, sas , fibre channel ? passive optical networks o epon, 10g - epon, gpon, 10g - pon ? ethernet o 1g, 10gbase - t/kr/lr/sr, and fcoe ? hd/sd/sdi video & surveillance ? pci express
_____________________________________________________________________________________________________________________________ _________________ dsc2010 page 2 mk - q - b - p - d - 120426 01 - 2 dsc2010 low - jitter configurable cmos oscillator pin description pin no. pin name pin type description 1 enable i enables outputs when high and disables when low 2 nc na leave unconnected or grounded 3 nc na leave unconnected or grounded 4 gnd power ground 5 fs0 i least significant bit for frequency selection 6 fs1 i most significant bit for frequency selection 7 nc na leave unconnected or grounded 8 output o cmos output 9 o s0 i least significant bit for output drive strength selectio n 10 o s1 i middle bit for output drive strength selection 11 nc na leave unconnected or grounded 12 vdd 2 power power supply 13 vdd power power supply 14 o s2 i most significant bit for output drive strength selection operational description the dsc201 0 is a cmos oscillator consisting of a mems resonator and a support pll ic . the cmos output is generated through independent 8 - bit programmable dividers from the output of the internal pll . the actual frequency o utput by the dsc201 0 is controlled by an internal pre - programmed memory (otp). this memory stores all coefficients required by the pll for up to four different frequencies. two contr ol pins (fs0 C fs 1 ) select the output frequency. discera supports custo mer defined versions of the dsc201 0 . standard frequency options are described in the following section s . when enable (pin 1) is floated or connected to v dd , the dsc201 0 is in operational mode. driving enable to ground wi ll disable the output driver ( hi - impedance mode). the dsc201 0 has programmable output drive strength. using three control pins (os0 - os 2 ) the drive strength can be adjusted to match circuit board impedances to reduce power supply noise, overshoot/undershoot and emi. table 1 displays t ypical rise / fall times for the output with a 15pf load capacitance as a function of these control pins at v dd =3.3v and room temperature. table 1. rise/fall times for drive strengths output drive strength bits [os 2 , os 1 , os 0 ] - default [ 111 ] 000 001 010 011 100 101 110 111 tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1 tf (ns) 2.5 2.4 2.4 2 .2 1.8 1.6 1. 4 1. 4
_____________________________________________________________________________________________________________________________ _________________ dsc2010 page 3 mk - q - b - p - d - 120426 01 - 2 dsc2010 low - jitter configurable cmos oscillator output clock frequencies table 2 lists the standard frequency configurations and the associated ordering information to be used in conjunct ion with the ordering code . customer defined combinations are available. table 2. pre - programmed pin - selectable output frequency c ombinations ordering info freq (mhz) freq select bits [fs1, fs0] C d efault is [ 11 ] 00 01 10 11 a 000 1 f out 27 24 148.5 74.25 a 0002 f out 155.52 106.25 156.25 125 a 0003 f out 25 75 125 1 50 a0004 f out 72 74.25 36 108 a0005 f out 27 50 0* 0* a0006 f out 16 13.56 0* 0* a000 7 f out 96 55 0* 0* a000 8 f out 25 50 0* 0* a000 9 f out 55.296 27.648 0* 0* a000 10 f out 27.648 55.296 0* 0* a000x f out contact factory for additional configurations. frequency select bit are weakly tied high so if left unconnected the default setting will be [11 ] and the device will output the associated frequency highlighted in bold . 0* C denotes invalid selection, output frequency is not specified.
_____________________________________________________________________________________________________________________________ _________________ dsc2010 page 4 mk - q - b - p - d - 120426 01 - 2 dsc2010 low - jitter configurable cmos oscillator absolute maximum ratings item min max unit condition supply voltage - 0.3 +4.0 v input voltage - 0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40 sec max. esd hbm mm cdm - 4000 400 1500 v note: 1000+ years of data retention on internal memory ordering code specifications (unless specified otherwise: t= 25 c , max cmos drive s trength ) notes: 1. pin 4 v dd should be filtered with 0.01uf capacitor . 2. t su is time to 100ppm stable output frequency after v dd is applied and outputs are enabled. 3. output waveform and test ci rcuit figures below define the parameters. 4. output is enabled if enable pad is floated or not connected. parameter condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current i dd en pin low C output is d isabled 2 1 23 ma frequency stability f includes frequency variations due to initial tolerance, temp. and power supply voltage 10 2 5 50 ppm aging f 1 year @ 25c 5 ppm startup time 2 t su t= 25c 5 ms input logic levels input logic hig h input logic low v ih v il 0.75 x v d d - - 0.25 x v dd v output disable time 3 t da 5 ns output enable time t en 20 n s pull - up resistor 4 pull - up exist s on all digital io 40 k cmos output supply current 4 i dd en pin high C output is enabled c l = 15 pf , f o =125 mhz 31 35 ma output logic levels output logic high output logic low v oh v ol i= 6ma 0.9xv dd - - 0.1xv dd v output transition time 3 rise time fall time t r t f 20% to 80% c l =15pf 1.1 1.3 2 2 n s frequency f 0 commercial/ i ndustrial temp range auto motive temp range 2.3 170 100 mhz output duty cycle sym 4 5 5 5 % period jitter j per f o = 125 mhz 3 ps rms integrated phase noise j cc 200khz to 20mhz @ 125mhz 100khz to 20mhz @ 125mhz 12khz to 20mhz @ 125mhz 0.3 0.38 1. 7 2 ps rms dsc2010 xxxxx freq (mhz) see freq. table - packing t: tape & reel : tube f i 2 package f : 3.2x2.5mm temp range e: - 20 to 70 i: - 40 to 85 l: - 40 to 105 m: - 55 to 125 stability 1: 50ppm 2: 25ppm 5: 10 ppm t
_____________________________________________________________________________________________________________________________ _________________ dsc2010 page 5 mk - q - b - p - d - 120426 01 - 2 dsc2010 low - jitter configurable cmos oscillator nominal performance parameters (unless specified otherwise: t=25 c, v dd =3.3 v) cmos phase jitter (integrated phase noise) output waveform: cmos v oh v ol v il 1/f o output enable t da t en t f t r v ih 0.0 0.5 1.0 1.5 2.0 2.5 0 200 400 600 800 1000 phase jitter (ps rms) low - end of integration bw: x khz to 20 mhz 25mhz - cmos 50mhz - cmos 106mhz - cmos 125mhz - cmos
_____________________________________________________________________________________________________________________________ _________________ dsc2010 page 6 mk - q - b - p - d - 120426 01 - 2 dsc2010 low - jitter configurable cmos oscillator solder reflow profile package dimensions 3.2 x 2.5 mm 14 lead plastic package disclaimer: micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in th is data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, micrel assumes no liability whatsoever, and mi crel disclaims any express or implied warranty relating to the sale and/or use of micrel products includ ing liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are inte nded for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers us e or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. micrel , inc. 2180 fortune drive , san jose, california 95131 usa phone: +1 (408) 944 - 0800 fax: +1 (408) 474 - 1000 email: hbwhelp @ micrel .com www.micrel.com msl 1 @ 260 c refer to jstd - 020c ramp - up rate (200 c to peak temp) 3 c/sec max. preheat time 150 c to 200 c 60 - 180 sec time maintained above 217 c 60 - 150 sec peak temperature 255 - 260 c time within 5 c of actual peak 20 - 40 sec ramp - down rate 6 c/sec max. time 25 c to peak temperature 8 min max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max. 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 60 - 150 sec 20 - 40 sec 60 - 180 sec 8 min max pre heat reflow cool time temperature ( c) 3c/sec max. 6c/sec max. 200 c 217 c 150 c 25 c 260 c 3c/sec max.
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